ABSTRACT FIFOs are frequently used to securely pass information starting with one clock space then onto the next offbeat clock area. Utilizing a FIFO to pass information starting with one clock area then onto the next clock space requires multi-nonconcurrent clock plan methods. There are numerous approaches to plan a FIFO wrong. There are numerous approaches to structure a FIFO right yet at the same t ime make it hard to appropriately combine and break down the plan. This paper will detail one strategy that is utilized to configuration, integrate and examine a protected FIFO between various clock spaces utilizing Gray code pointers that are synchronized into an alternate clock area before testing for "FIFO full" or "FIFO vacant" conditions. The completely coded, incorporated and investigated RTL Verilog model is incorporated.