Abstract Electrocardiogram (ECG) is non-stationary, non-periodic real-time signal. It is provided to use full electrical information about heart functioning. It means by the analysis of ECG signal; we can identify any living person's hearts are working properly or not. In recent years there is a huge demand for the reduction of size and power of portable devices used for monitoring critical signals such as ECG. The technical advancements in VLSI have created a huge impact on biomedical signal processing. VLSI circuits working at high speed and these can be designed to consume less area and power. Especially for ECG signal denoising, digital filters such as FIR and IIR are used in most of the applications. Finite Impulse Filters (FIR) are used widely compared to IIR filters because of their good stability and high order. In this paper, FIR filter with modified Vedic multiplier-based architecture is introduced to carry out ECG signal denoising application. In this paper at first resource-efficient Vedic multiplier is introduced which is around 55% area-efficient for 8 bit, 15% efficient in terms of delay, and 45% efficient in terms of power in comparisons of the latest design proposed in 2020. Then with the help of a modified Vedic multiplier, FIR is developed which is also efficient in terms of resources. It has 40.5% better ADP and around 20% better APP. This latest design of the filter is much helpful for ECG signal denoising.