Abstract: Redundant Binary Partial Product Generators are used to minimize, without any increase in the delayed partial product development block by one row, the maximum height of the partial product array generated by radix- 16 Modified Booth Encoded multiplier. The optimization for binary radix-16 (modified booth coded) multipliers is defined in this project to decrease the maximum volume of the partial product columns to [n/4], with n = 64-bit non-signed operand. This compares [(n + 1)/4] with the normal maximum height. Thus the overall height of a single device is limited. This multiplier improves ALU and processors efficiency. In contrast to the traditional booth multiplier, we test the suggested solution. In terms of field, delay and control, the logical synthesis showed its effectiveness. Using Verilog, the project will be built. The Simulation and Synthesis Xilinx ISE method is used.