Abstract—Hardware Trojan (HT) can be introduced by an adversary at an untrusted design or fabrication house. Depending on the interests of the adversary the HT can cause change in functionality, denial-ofservice, and information leakage or reliability reduction. In the existing system, a self-referencing based HT detection method using path delays which eliminates the requirement of golden ICs, is used. Further, we developed a procedure to select paths that minimizes the effect of both inter-die and intra-die PV. We have used topologically symmetric paths to mitigate inter-die variations and selected closer paths to exploit the spatial correlation to reduce the impact of intra-die variations. In the proposed system, Low density parity check with majority logic gate is used to predict the unknown post silicon errors occur in the integrated chips. Those small errors produce a large variation in the development of complex circuitry which utilizes maximum space of the FPGA. The proposed system uses Quartus II software and provides the simulation model showing the normal establishment of data transfer and Hardware Trojan affected system separately.