Abstract: A novel self-pipelining technique is developed in this work. Which includes proper synchronization between the stages for high-speed and low-power multiplication is defined. To accomplish the proposed self-pipelining process, the true and complementary clock inputs are added alternative to each corresponding self-latching step. First was designed a 4-b×4-b self-pipeline Wallace-tree multiplier based on the above idea. The key purpose of our proposed approach is to minimize the amount of transistors relative to the current system such that we build circuits where the complete adder is made of multiplexer depending on XOR that is used in multiplexers. Comparing between the current competitive designs to our proposed design shows that supremacy results.