AN EFFICIENT DENOISING HARDWARE ARCHITECTURE OF CSA-FIR FILTER FOR REAL TIME ECG SIGNALS
European Journal of Molecular & Clinical Medicine,
2020, Volume 7, Issue 10, Pages 3502-3513
Abstract
In the recent years there is a huge demand for reduction in size and power of portable devices used for monitoring critical signals such as ECG. The technical advancements in VLSI has created a huge impact on biomedical signal processing. VLSI circuits working at high speed can be designed in order to consume less area and power. Especially for ECG signal denoising, digital filters such as FIR and IIR are used in most of the applications. Finite Impulse Filters (FIR) is used widely compared to IIR filters because of their good stability and high order. In this paper, FIR filter with modified carry save adder-based MACarchitectureis introduced to carryout ECG signal denoising application. The input raw ECG signal collected from MIT-PhysionetArrhythmia data base is read using MATLAB and coefficients are generated. resource efficient FIR filter is designedby using carry save adder.Therefore, a carry save adder circuit can be invented with minimal area and power consumption. It is evident that the power line interference noise has been removed and denoised ECG signals have been obtained. And these noises have been removed from ECG MIT-BIH Arrhythmia database (record# 100,101,102 &103). It has 14.98 % less area, 8.83% lees power, 26.24% less delay, 22.48% less APP and 37.29% less ADP.
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