Online ISSN: 2515-8260

Keywords : DSP


Noise Removal in ECG Signal Using Digital Filters

N. Sasirekha; P. Vivek Karthick; T. Premakumari; J. Harirajkumar; S. Aishwarya

European Journal of Molecular & Clinical Medicine, 2020, Volume 7, Issue 2, Pages 5145-5149

The Electro Cardio Gram (ECG) is a parametric index to diagnose heart diseases. During the process of acquisition of the ECG signals, it is added up by large amount of noise, which affects the patient diagnosis with respect to telemedicine. The noisy ECG signals have drift in baseline, motion electrodes artefacts, interference of line, muscle contraction noise, etc. Noise reduction is accomplished by making using of adaptive filter which employs wavelet transform. Computer simulation results are shown for the improvement in performance. This methodology adapted successfully removes various types of noise with Signal to noise ratio (SNR). The impact of noise and removal of it are shown in the waveforms and the methodology adopted has produced 82% improvement on the SNR of de-noised signals.

VLSI DESIGNS VERIFICATION OF DSP

K.DEEPA, Y.JALAJAKSHI, P.CHANDRASHEKAR

European Journal of Molecular & Clinical Medicine, 2017, Volume 4, Issue 1, Pages 129-135

Foregg, Digital Signal Processing (DSP) is growing with sophisticated capabilities in locally
accessible space applications, thanks to the use of Field Programmable Gate Arrays (FPGA)
and Specific Integrated Circuits for Application (ASICs). Proof of these perplexing systems is
being checked inside tiny timetables and characteristics. It is critical to conduct strict
functional monitoring in order to ensure that these systems operate reliably in all conceivable
run-time scenarios. Even with the use of cutting-edge Hardware Verification Languages
(HVLs) and approaches such as System-Virology (SV) and Universal Verification
Methodology (UVM), improving a mechanized self-checking validation state or test seats,
including the age of bit-exact genius reference values, is a complex and time-consuming task.
This article investigates a utilitarian check method for the DSP-based VLSI setup utilizing SV
and Mat lab. The design of the verify situation, method for integrating Mat lab with SV-based
validation condition, and age of bit-accurate genius references are continuously examined in
detail, in addition to two contextual investigations